1. Field of the Invention
The present invention generally relates to a synchronizing device for real-time USB audio data transmission and, more particularly, to a synchronizing device capable of overcoming asynchronicity of data transmission between the USB host and external devices.
2. Description of the Prior Art
FIG. 1 is a circuit block of a conventional synchronizing device for real-time USB audio data transmission. Referring to FIG. 1, a conventional synchronizing device for real-time USB audio data transmission 1 comprises a difference adder unit 2, a frame calibrating register unit 3, a calibrating mapping unit 4, a calibrating pulse generating unit 5, a frequency divider 6, a start-of-frame countdown unit 7 and three adder units 8. In FIG. 1, the first clock signal CLKOUT is a clock signal issued by the frequency divider 6 into which the second clock signal CLK4X is input. The frequency dividing factor selection signal ADJSIGN determines the fractional relation (1/3.5 or 1/4.5) of the frequency divider 6. The calibrating pulse signal ADJLOAD determines that the first clock signal CLKOUT equals to the second clock signal CLK4X divided by 3.5 or 4.5 at some timing and by 4 at other timing.
When the target frequency is 12.288 MHz, the initial value of the start-of-frame countdown unit 7 is 12288. The start-of-frame countdown unit 7 receives the start-of-frame signal SOFP and the first clock signal CLKOUT, wherein the start-of-frame signal SOFP is a start-of-frame sent by the USB host (not shown) and a clock signal decoded by a serial interface engine (not shown) to be used as a synchronous signal. When the start-of-frame signal SOFP signal is input into the start-of-frame countdown unit 7, countdown begins and will not stop until a next start-of-frame signal SOFP signal is received. Meanwhile, the start-of-frame countdown unit 7 sends the clock number difference DIFF to the frame calibrating register unit 3 and the difference adder unit 2, and resets the value back to 12288.
Since the time for the first clock signal CLKOUT to count a start-of-frame is not exactly an integral multiple of the clock cycle of the first clock signal CLKOUT, indicating that there is time difference in each clock cycle of the first clock signal CLKOUT within each start-of-frame time, the accumulative time difference may exceed a clock cycle of the first clock signal CLKOUT after several start-of-frame times. As a result, the target frequency difference will become significant and a difference adder unit 2 is required to eliminate the accumulative error.
The frame calibrating register unit 3 records the clock number difference DIFF value in a previous start-of-frame time and inputs the clock number difference DIFF value into the calibrating mapping unit 4 to a frequency dividing factor selection signal ADJSIGN and an adjusted number value ADJMAP. The adjusted number value ADJMAP controls the calibrating pulse generating unit 5 to issue a calibrating pulse signal ADJLOAD signal. The calibrating pulse signal ADJLOAD and the frequency dividing factor selection signal ADJSIGN determine the timing for the frequency divider 6 to be divided by 3.5 or 4.5.
In the prior art device, a difference of only 12 clock cycles of the first clock signal CLKOUT appears when the target frequency is 12.288 MHz and the input frequency of 49.2 MHz is divided. However, in a practical USB circuit, a 49.2-MHz phase-locked loop circuit is required. For example, when the target frequency is 12.288 MHz, a difference of 288 clock cycles of the first clock signal CLKOUT appears after a 48-MHz clock is frequency divided. Therefore, the mapping table must be enhanced and a larger difference appears between the output frequency and the target frequency.
Therefore, there exists a need in providing a synchronizing device for USB real-time audio data transmission capable of overcoming asynchronicity of data transmission between the USB host and external devices.